In order to perform the transfer of data between a memory LSI (Large Scale Integration) and a MPU (Microprocessor) or the like at high speed (high frequency), it is necessary to impedance match the transmission system and to suppress distortion of the transfer waveform caused by reflection. It is known to control the impedance of the output driver of a high-speed synchronous SRAM (Static Random Access Memory) so as to provide an impedance equal to the resistance value of a resistive element connected to a dedicated LSI pin, for the purpose of impedance matching.
The controlling or adjusting of output impedance for data transfer has been disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 10(1998)-242835. In the referenced patent publication, an output impedance adjustment transistor and a through-rate adjustment transistor are provided in order to control output impedance. More specifically, a shot pulse is applied to the gate of the through-rate adjustment transistor to control a rise time interval and an output voltage level as determined by the impedance adjustment transistor.
Thus, the need exists for a semiconductor device, system, and method that provides data transfer at high frequency using impedance matching, and that reduces the wiring and complexity of the same.